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A multi level functional verification of multistage interconnection network for MPSOC.
Yassine Aydi
Ramzi Tligue
Maissa Elleuch
Mohamed Abid
Jean-Luc Dekeyser
Published in:
ICECS (2009)
Keyphrases
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interconnection networks
multistage
functional verification
lot sizing
dynamic programming
single stage
formal verification
stochastic programming
fault tolerant
low latency
image processing
low cost
hardware software