Jae Young Hur

ORCID

Publication Activity (10 Years)

Years Active: 2007-2023
Publications (10 Years): 10

Top Venues

IEEE Access

IEICE Trans. Inf. Syst.

IEICE Electron. Express

MCSoC

Delft University of Technology, Netherlands (PHD)

Education History

Delft University of Technology, Netherlands

PHD

Publications

Tran Dai Duong, Jae Young Hur
Page-Size Aware Buddy Allocator With Unaligned Range Supports for TLB Coalescing. IEEE Access 11 (2023)
Minshin Cho, Jae Young Hur, Wooyoung Jang
Clean-prefetcher: look-ahead prefetching without cache pollution. IEICE Electron. Express 18 (6) (2021)
Taejin Park, Jae Young Hur, Wooyoung Jang
TLC STT-MRAM aware LLC for multicore processor. IEICE Electron. Express 17 (24) (2020)
Jae Young Hur, Joonho Kong
Page Table Compaction for TLB Coalescing. IEEE Access 8 (2020)
Joonho Kong, Jae Young Hur
Near-Threshold L1 Data Cache for Yield Management Under Process Variations. IEEE Access 8 (2020)
Jae Young Hur
Virtual Address Remapping with Configurable Tiles in Image Processing Applications. IEICE Trans. Inf. Syst. (2) (2020)
Jae Young Hur
Block Level TLB Coalescing for Buddy Memory Allocator. IEICE Trans. Inf. Syst. (10) (2019)
Jae Young Hur
Contiguity Representation in Page Table for Memory Management Units. IEEE Trans. Very Large Scale Integr. Syst. 27 (1) (2019)
Jae Young Hur, Sang Woo Rhim, Beom Hak Lee, Wooyoung Jang
Adaptive Linear Address Map for Bank Interleaving in DRAMs. IEEE Access 7 (2019)
Jae Young Hur
Representing Contiguity in Page Table for Memory Management Units. MCSoC (2017)
Jae Young Hur, Kees Goossens, Lotfi Mhamdi, Muhammad Aqeel Wahlah
Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays. IET Comput. Digit. Tech. 6 (6) (2012)
Jae Young Hur, Todor P. Stefanov, Stephan Wong, Kees Goossens
Customisation of on-chip network interconnects and experiments in field-programmable gate arrays. IET Comput. Digit. Tech. 6 (1) (2012)
Thomas Marconi, Jae Young Hur, Koen Bertels, Georgi Gaydadjiev
A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices. SASP (2010)
Jae Young Hur, Stephan Wong, Todor P. Stefanov
Design Trade-offs in Customized On-chip Crossbar Schedulers. J. Signal Process. Syst. 58 (1) (2010)
Min Cheol Park, Moon Kyu Kwak, Hye Sung Cho, Kahp Y. Suh, Jae Young Hur, Sang-Hyun Park
Yeast on a Chip - Single-cell Analyses of MAPK Signaling Pathways in Saccharomyces Cerevisiae using Cell Chips. BIODEVICES (2) (2008)
Kees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects. NOCS (2008)
Jae Young Hur, Todor P. Stefanov, Stephan Wong, Stamatis Vassiliadis
Systematic Customization of On-Chip Crossbar Interconnects. ARC (2007)
Jae Young Hur, Stephan Wong, Stamatis Vassiliadis
Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs. ARC (2007)
Jae Young Hur, Todor P. Stefanov, Stephan Wong, Stamatis Vassiliadis
Customizing Reconfigurable On-Chip Crossbar Scheduler. ASAP (2007)

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Publication Activity (10 Years)

Top Topics

Top Venues

Jae Young Hur