TLC STT-MRAM aware LLC for multicore processor.
Taejin ParkJae Young HurWooyoung JangPublished in: IEICE Electron. Express (2020)
Keyphrases
- cell processor
- random access memory
- memory management
- design considerations
- high end
- multicore processors
- level parallelism
- high speed
- operating system
- parallel processing
- computing power
- highly parallel
- computer systems
- computation intensive
- multiprocessor systems
- low voltage
- computer architecture
- distributed memory
- low cost
- single chip
- database management systems
- shared memory
- class imbalance