Hyun-Wook Lim

Publication Activity (10 Years)

Years Active: 2015-2023
Publications (10 Years): 8

Top Topics

Fingerprint Authentication

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Very Large Scale Integr. Syst.

Publications

San-Ho Byun, Heejin Lee, Tae-Gyun Song, Jinchul Lee, Jongmin Baek, Gyeongmin Ha, Seunghoon Baek, Yeongmin Kim, Won-Gab Jung, Hyun-Wook Lim, Siwoo Kim, Jae-Youl Lee
A 45.8dB-SNR 120fps 100pF-Load Self-Capacitance Touch-Screen Controller with Enhanced In-Band Common Noise Immunity Using Noise Antenna Reference. ISSCC (2023)
Kyungho Ryu, Ji-Yong Jeong, Jung-Pil Lim, Kil-Hoon Lee, Kyongho Kim, Yongil Kwon, Seongjong Yoo, Siwoo Kim, Hyun-Wook Lim, Jae-Youl Lee
A Source-Driver IC Including Power-Switching Fast-Slew-Rate Buffer and 8Gb/s Effective 3-Tap DFE Receiver Achieving 4.9mV DVRMS and 17V/ps Slew Rate for 8K Displays and Beyond. ISSCC (2023)
Ji-Soo Chang, Eunsang Jang, Youngkil Choi, Moonkyu Song, Sanghyo Lee, Gi-Jin Kang, Junho Kim, Uijong Song, Chang-Yeon Cho, Giyeong Ko, Hyunseok Hwang, Junseo Lee, Han-Sol Lee, Yong-Il Kwon, Kyungduck Seo, Taeseon Kim, Hyun-Wook Lim, Seongwook Song, Jae-Youl Lee, Sung Ung Kwak
A 1.05-A/m Minimum Magnetic Field Strength Single-Chip, Fully Integrated Biometric Smart Card SoC Achieving 792.5-ms Transaction Time With Anti-Spoofing Fingerprint Authentication. IEEE J. Solid State Circuits 58 (1) (2023)
Tae-Jin Kim, Jae-Woo Park, Hyun-Wook Lim, Jae-Youl Lee, Jung-Hoon Chun
An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires. IEEE J. Solid State Circuits 57 (3) (2022)
Un-Ki Park, Min-Sik Kim, Jong-Hyuk Lee, Hyeon-Su Park, Hyun-Wook Lim, Jae-Youl Lee
A Novel Efficient Power Saving Method for Always-On Display. ICCE (2022)
Joohyuk Yum, Yong-Hoon Yu, Hyeonsu Park, Hyun-Wook Lim, Jae-Youl Lee
A Novel Method to Reduce Luminance Variation Due to IR-drop in Active Matrix OLED Displays. ICCE (2020)
Kyungho Ryu, Kil-Hoon Lee, Jung-Pil Lim, Jinho Kim, Han Su Pae, Junho Park, Hyun-Wook Lim, Jae-Youl Lee
An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits. IEEE Trans. Very Large Scale Integr. Syst. 28 (11) (2020)
Hyun-Wook Lim, Sung-Won Choi, Jeong-Keun Ahn, Woong-Ki Min, Sang-Kyu Lee, Chang-Hoon Baek, Jae-Youl Lee, Gyoo-Cheol Hwang, Young-Hyun Jun, Bai-Sun Kong
A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface. IEEE J. Solid State Circuits 52 (6) (2017)
Hyun-Wook Lim, Sung-Won Choi, Sang-Kyu Lee, Chang-Hoon Baek, Jae-Youl Lee, Gyoo-Cheol Hwang, Bai-Sun Kong, Young-Hyun Jun
10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface. ISSCC (2015)