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An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires.
Tae-Jin Kim
Jae-Woo Park
Hyun-Wook Lim
Jae-Youl Lee
Jung-Hoon Chun
Published in:
IEEE J. Solid State Circuits (2022)
Keyphrases
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high speed
higher level
real time
neural network
website
computer simulation
data acquisition
user input