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A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface.

Hyun-Wook LimSung-Won ChoiJeong-Keun AhnWoong-Ki MinSang-Kyu LeeChang-Hoon BaekJae-Youl LeeGyoo-Cheol HwangYoung-Hyun JunBai-Sun Kong
Published in: IEEE J. Solid State Circuits (2017)
Keyphrases
  • decision feedback
  • high speed
  • user interface
  • user friendly
  • memory usage
  • computing power
  • friendly interface
  • computational power
  • neural network
  • memory requirements
  • random access