Hye-Seung Yu

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 5

Top Topics

Nearest Neighbor

Statistical Significance

Null Hypothesis

Top Venues

IEEE J. Solid State Circuits

Publications

Daehyun Kwon, Heon Su Jeong, Jaemin Choi, Wijong Kim, Jae Woong Kim, Junsub Yoon, Jungmin Choi, Sanguk Lee, Hyunsub Norbert Rie, Jin-il Lee, Jongbum Lee, Taeseong Jang, JunHyung Kim, Sanghee Kang, Jung-Bum Shin, Yanggyoon Loh, Chang-Yong Lee, Junmyung Woo, Hye-Seung Yu, Changhyun Bae, Reum Oh, Young-Soo Sohn, Changsik Yoo, Jooyoung Lee
A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL. ISSCC (2023)
Sung Joo Park, Jonghoon J. Kim, Kun Joo, Young-Ho Lee, Kyoungsun Kim, Young-Tae Kim, Woo-Jin Na, IkJoon Choi, Hye-Seung Yu, Wonyoung Kim, Ju-Yeon Jung, Jaejun Lee, Dohyung Kim, Young-Uk Chang, Gong-Heum Han, Hangi-Jung, Sunwon Kang, Jeonghyeon Cho, Hoyoung Song, Tae-Young Oh, Young-Soo Sohn, SangJoon Hwang, JooYoung Lee
Industry's First 7.2 Gbps 512GB DDR5 Module. HCS (2021)
Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Hyunui Lee, Seok-Yong Kang, Young-Soo Sohn, Jung-Hwan Choi, Yong-Cheol Bae, Seong-Jin Jang, Gyo-Young Jin
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution. IEEE J. Solid State Circuits 52 (1) (2017)
Hyunui Lee, Sukyong Kang, Hye-Seung Yu, Won-Joo Yun, Jae-Hun Jung, Sungoh Ahn, Wang-Soo Kim, Beomyong Kil, Yoo-Chang Sung, Sang-Hoon Shin, Yong-Sik Park, Yong-Hwan Kim, Kyung-Woo Nam, Indal Song, Kyomin Sohn, Yong-Cheol Bae, Jung-Hwan Choi, Seong-Jin Jang, Gyo-Young Jin
Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM). A-SSCC (2016)
Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh, Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Kyung-Woo Nam, Seouk-Kyu Choi, Jaewook Lee, Uksong Kang, Young-Soo Sohn, Jung-Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Gyo-Young Jin
18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution. ISSCC (2016)
Jong-Chul Lim, Hye-Seung Yu, Jae-Suk Choi, Soo-Won Kim
An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin. ASP-DAC (2005)