A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.
Kyomin SohnWon-Joo YunReum OhChi-Sung OhSeong-Young SeoMin-Sang ParkDong-Hak ShinWon-Chang JungSang-Hoon ShinJe-Min RyuHye-Seung YuJae-Hun JungHyunui LeeSeok-Yong KangYoung-Soo SohnJung-Hwan ChoiYong-Cheol BaeSeong-Jin JangGyo-Young JinPublished in: IEEE J. Solid State Circuits (2017)