Hosahalli R. Srinivas

Publication Activity (10 Years)

Years Active: 1991-1999
Publications (10 Years): 0

Publications

Hosahalli R. Srinivas, Keshab K. Parhi
A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture. J. VLSI Signal Process. 21 (1) (1999)
S. K. Misra, R. K. Kolagotla, Hosahalli R. Srinivas, J. C. Mo, Marc S. Diamondstein
VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay. VLSI Design (1998)
Hosahalli R. Srinivas, Keshab K. Parhi, Luis A. Montalvo
Radix 2 Division with Over-Redundant Quotient Selection. IEEE Trans. Computers 46 (1) (1997)
Mohit K. Prasad, Paul D'Arcy, Arup Gupta, Marc S. Diamondstein, Hosahalli R. Srinivas
Half-rate GSM vocoder implementation on a dual mac digital signal processor. ICASSP (1997)
Hosahalli R. Srinivas, Keshab K. Parhi
A Fast Radix-4 Division Algorithm and Its Architecture. IEEE Trans. Computers 44 (6) (1995)
Hosahalli R. Srinivas, Keshab K. Parhi
A floating point radix 2 shared division/square root chip. ICCD (1995)
W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi
A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging. VLSI Design (1995)
Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi
A C-testable carry-free divider. IEEE Trans. Very Large Scale Integr. Syst. 2 (4) (1994)
Hosahalli R. Srinivas, Keshab K. Parhi
A Fast Radix-4 Division Algorithm. ISCAS (1994)
Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi
A C-Testable Carry-Free Divider. ICCD (1993)
Hosahalli R. Srinivas, Keshab K. Parhi
High-speed VLSI arithmetic processor architectures using hybrid number representation. J. VLSI Signal Process. 4 (2-3) (1992)
Hosahalli R. Srinivas, Keshab K. Parhi
High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation. ICCD (1991)