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VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay.

S. K. MisraR. K. KolagotlaHosahalli R. SrinivasJ. C. MoMarc S. Diamondstein
Published in: VLSI Design (1998)
Keyphrases
  • vlsi implementation
  • vlsi architecture
  • real time
  • computer vision
  • fir filters
  • feature selection
  • image processing
  • denoising