Harald Michalik

Publication Activity (10 Years)

Years Active: 1986-2022
Publications (10 Years): 12

Top Topics

Safety Critical

Data Processing

Equal Error Rate

Top Venues

Publications

Alexander Dörflinger, Benedikt Kleinbeck, Mark Albers, Harald Michalik, Martin Moya
A Framework for Fault Tolerance in RISC-V. DASC/PiCom/CBDCom/CyberSciTech (2022)
Alexander Dörflinger, Mark Albers, Benedikt Kleinbeck, Yejun Guan, Harald Michalik, Raphael Klink, Christopher Blochwitz, Anouar Nechi, Mladen Berekovic
A comparative survey of open-source application-class RISC-V processor implementations. CF (2021)
Alexander Dörflinger, Yejun Guan, Sören Michalik, Sönke Michalik, Jamin Naghmouchi, Harald Michalik
ECC Memory for Fault Tolerant RISC-V Processors. ARCS (2020)
Alexander Dörflinger, Mark Albers, Björn Fiethe, Harald Michalik, Mischa Möstl, Johannes Schlatow, Rolf Ernst
Demonstrating Controlled Change for Autonomous Space Vehicles. AHS (2019)
Mischa Möstl, Alexander Dörflinger, Mark Albers, Harald Michalik, Rolf Ernst
Self-Adaptation for Availability in CPU-FPGA Systems Under Soft Errors. AHS (2019)
Harald Michalik, Holger Dinse
Electronic Automotive and Aerospace Systems - a Master Programme on electronics design for safety critical applications. EWME (2018)
Alexander Dörflinger, Mark Albers, Björn Fiethe, Harald Michalik
Hardware Acceleration in Genode OS Using Dynamic Partial Reconfiguration. ARCS (2018)
Alexander Dörflinger, Mark Albers, Johannes Schlatow, Björn Fiethe, Harald Michalik, Phillip Keldenich, Sándor P. Fekete
Hardware and Software Task Scheduling for ARM-FPGA Platforms. AHS (2018)
Alexander Dörflinger, Björn Fiethe, Harald Michalik, Sándor P. Fekete, Phillip Keldenich, Christian Scheffer
Resource-efficient dynamic partial reconfiguration on FPGAs for space instruments. AHS (2017)
Holger Michel, Hipólito Guzmán-Miranda, Alexander Dörflinger, Harald Michalik, Miguel Aguirre Aguirre Echánove
SEU fault classification by fault injection for an FPGA in the space instrument SOPHI. AHS (2017)
Tobias Lange, Björn Fiethe, Holger Michel, Harald Michalik, Kinga Albert, Johann Hirzberger
On-board processing using reconfigurable hardware on the solar orbiter PHI instrument. AHS (2017)
Holger Michel, Adrian Belger, Tobias Lange, Björn Fiethe, Harald Michalik
Read back scrubbing for SRAM FPGAs in a data processing unit for space instruments. AHS (2015)
Sándor P. Fekete, Björn Fiethe, Stephan Friedrichs, Harald Michalik, Christos Orlis
Efficient reconfiguration of processing modules on FPGAs for space instruments. AHS (2014)
Antonis M. Paschalis, Harald Michalik, Nektarios Kranitis, Celia López-Ongil, Pedro Reviriego Vasallo
Dependable reconfigurable space systems: Challenges, new trends and case studies. IOLTS (2014)
Holger Michel, Frank Bubenhagen, Kai Grurmann, Tobias Lange, Björn Fiethe, Harald Michalik
Worst case error rate predictions and mitigation schemes for Virtex-4 FPGAs on solar orbiter. AHS (2013)
Frank Bubenhagen, Björn Fiethe, Tobias Lange, Harald Michalik, Holger Michel
Reconfigurable platforms for Data Processing on scientific space instruments. AHS (2013)
Gang Zhou, Li Li, Harald Michalik
Complexity Analysis of Finite Field Digit Serial Multipliers on FPGAs. ARC (2012)
Rolf Ernst, Harald Michalik, Peter Rüffer
Institut für Datentechnik und Kommunikationsnetze - Mitgestaltung der Informatik in Braunschweig. 40 Jahre Informatik @ Braunschweig (2012)
Holger Michel, Adrian Belger, Frank Bubenhagen, Björn Fiethe, Harald Michalik, Wayne Sullivan, Alex Wishart, Jørgen Ilstad
The SoCWire protocol (SoCP): A flexible and minimal protocol for a Network-on-Chip. AHS (2012)
Björn Fiethe, Frank Bubenhagen, Tobias Lange, Harald Michalik, Holger Michel, Joachim Woch, Johann Hirzberger
Adaptive hardware by dynamic reconfiguration for the Solar Orbiter PHI instrument. AHS (2012)
Holger Michel, Frank Bubenhagen, Björn Fiethe, Harald Michalik, Björn Osterloh, Wayne Sullivan, Alex Wishart, Jørgen Ilstad, Sandi Habinc
AMBA to SoCWire network on Chip bridge as a backbone for a Dynamic Reconfigurable Processing unit. AHS (2011)
Björn Osterloh, Harald Michalik, Björn Fiethe, Frank Bubenhagen
Architecture verification of the SoCWire NoC approach for safe dynamic partial reconfiguration in space applications. AHS (2010)
Gang Zhou, Harald Michalik
Comments on "A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Field". IEEE Trans. Computers 59 (7) (2010)
Gang Zhou, Harald Michalik, László Hinsenkamp
Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 18 (7) (2010)
Gang Zhou, Harald Michalik, László Hinsenkamp
Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs. ARC (2009)
Yannick Dadji Foyet, Harald Michalik, Tobias Möglich
Parallel Architecture For Real Time Control System Based On The IEEE1394 Standard. PDPTA (2009)
Björn Osterloh, Harald Michalik, Björn Fiethe
SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs. ARCS (2009)
Björn Osterloh, Harald Michalik, Sandi Habinc, Björn Fiethe
Dynamic Partial Reconfiguration in Space Applications. AHS (2009)
Yannick Dadji, Jochen Maaß, Harald Michalik, Tobias Möglich, Nnamdi Kohn, J. Uwe Varchmin
Networked Architecture for Distributed PC-based Robot Control Systems. ARCS (2008)
Gang Zhou, Li Li, Harald Michalik
Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS. FPL (2008)
Björn Osterloh, Harald Michalik, Björn Fiethe, Karel Kotarowski
SoCWire: A Network-on-Chip Approach for Reconfigurable System-on-Chip Designs in Space Applications. AHS (2008)
Björn Osterloh, Harald Michalik, Björn Fiethe, Frank Bubenhagen
Enhancements of reconfigurable System-on-Chip Data Processing Units for Space Application. AHS (2007)
Gang Zhou, Harald Michalik, László Hinsenkamp
Efficient and High-Throughput Implementations of AES-GCM on FPGAs. FPT (2007)
Björn Fiethe, Harald Michalik, C. Dierker, Björn Osterloh, Gang Zhou
Reconfigurable system-on-chip data processing units for space imaging instruments. DATE (2007)
Peter Rueffer, Harald Michalik, Fritz Gliem, Frank Rabe
Image data compressor for Huygens' DISR instrument compared to state of the art compression schemes. IGARSS (2004)
E. Krahn, Fritz Gliem, Harald Michalik, Peter Rüffer
Der Instrumentenrechner der Halley Multicolour Camera. ARCS (1986)