Gil-Cho Ahn

Publication Activity (10 Years)

Years Active: 1996-2024
Publications (10 Years): 22

Top Topics

Analog To Digital Converter

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEICE Electron. Express

Publications

Kang-Il Cho, Jun-Ho Boo, Jae-Geun Lim, Gil-Cho Ahn
A CMOS Analog Front-End for Hall Sensor Readout IC. ICEIC (2024)
Mi-Ji Go, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Seong-Bo Park, Byeongho Yu, Won-Jun Cho, Gil-Cho Ahn
A 12-bit 3-MS/s Synchronous SAR ADC With a Hybrid RC DAC. ISOCC (2023)
Seong-Bo Park, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Won-Jun Cho, Gil-Cho Ahn
A Second-Order DT Delta-Sigma Modulator with Noise-Shaping SAR Quantizer. ISOCC (2023)
Ho-Jin Kim, Jun-Ho Boo, Kang-Il Cho, Yong-Sik Kwak, Gil-Cho Ahn
A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC. IEEE Trans. Circuits Syst. II Express Briefs 70 (2) (2023)
Hyoung-Jung Kim, Jae-Hyuk Lee, Jae-Geun Lim, Jun-Ho Boo, Ho-Jin Kim, Seong-Bo Park, Youngdon Choi, Jung-Hwan Choi, Gil-Cho Ahn
A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor. ISOCC (2022)
Yong-Sik Kwak, Ho-Jin Kim, Kang-Il Cho, Jun-Ho Boo, Gil-Cho Ahn
103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction Technique. A-SSCC (2021)
Ju-Hye Han, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Jae Sang Kim, Gil-Cho Ahn
A 96dB Dynamic Range 2kHz Bandwidth 2nd Order Delta-Sigma Modulator Using Modified Feed-Forward Architecture With Delayed Feedback. IEEE Trans. Circuits Syst. II Express Briefs 68 (5) (2021)
Jun-Ho Boo, Kang-Il Cho, Ho-Jin Kim, Jae-Geun Lim, Yong-Sik Kwak, Seung-Hoon Lee, Gil-Cho Ahn
A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, -0.12% for Battery-Monitoring Applications. IEEE J. Solid State Circuits 56 (4) (2021)
Tae-Gwan Kim, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, Gil-Cho Ahn
A Third-Order DT Delta-Sigma Modulator With Noise-Coupling Technique. ISOCC (2020)
Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, Jun-Sang Park, Seung-Hoon Lee, Gil-Cho Ahn
A 10-b 900-MS/s Single-Channel Pipelined-SAR ADC Using Current-Mode Reference Scaling. A-SSCC (2020)
Jun-Sang Park, Je-Min Jeon, Jun-Ho Boo, Jae-Hyuk Lee, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn, Seung-Hoon Lee
A 2.2mW 12-bit 200MS/s 28nm CMOS Pipelined SAR ADC with Dynamic Register-Based High-Speed SAR Logic. A-SSCC (2020)
Jun-Ho Boo, Kang-Il Cho, Ho-Jin Kim, Jae-Geun Lim, Yong-Sik Kwak, Seung-Hoon Lee, Gil-Cho Ahn
A Single-Trim Switched Capacitor CMOS Bandgap Reference with a 3σ Inaccuracy of +0.02%, -0.12% for Battery Monitoring Applications. VLSI Circuits (2020)
Jun-Sang Park, Tai-Ji An, Gil-Cho Ahn, Seung-Hoon Lee
A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOS Pipelined SAR ADC Based on Energy-Efficient Switching and Shared Ring Amplifier. IEEE Trans. Circuits Syst. II Express Briefs (7) (2019)
Kang-Il Cho, Yong-Sik Kwak, Ho-Jin Kim, Jun-Ho Boo, Seung-Hoon Lee, Gil-Cho Ahn
A 10-b 320-MS/s Dual-Residue Pipelined SAR ADC with Binary Search Current Interpolator. CICC (2019)
Jun-Young Kil, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, Gil-Cho Ahn
A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application. ISOCC (2019)
Himchan Park, Qiwei Huang, Changzhi Yu, Seulki Kim, Gil-Cho Ahn, Jinwook Burm
Two CMOS time to digital converters using successive approximation register logic. IEICE Electron. Express 15 (22) (2018)
Tai-Ji An, Moon-Sang Hwang, Won-Jun Choe, Gil-Cho Ahn, Seung-Hoon Lee
Area-Efficient Time-Shared Digital-to-Analog Converter With Dual Sampling for AMOLED Column Driver IC's. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Seung-Hoon Lee, Gil-Cho Ahn
A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta-Sigma Modulator Using Source-Follower-Based Integrators. IEEE J. Solid State Circuits 53 (10) (2018)
Kang-Il Cho, Yong-Sik Kwak, Ho-Jin Kim, Gil-Cho Ahn
A 101 dB dynamic range, 2 kHz bandwidth delta-sigma modulator with a modified feed-forward architecture. IEICE Electron. Express 15 (21) (2018)
Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn
A 1.8 V 89.2 dB dynamic range delta-sigma modulator using an op-amp dynamic current biasing technique. IEICE Electron. Express 14 (21) (2017)
Bum-Sik Chung, Hyeong-Kyu Kim, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn
Analog front-end for EMG acquisition system. ISOCC (2017)
Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Seung-Hoon Lee, Gil-Cho Ahn
A 72.9-dB SNDR 20-MHz BW 2-2 discrete-time sturdy MASH delta-sigma modulator using source-follower-based integrators. A-SSCC (2017)
Mi-rim Kim, Young-Ouk Kim, Yong-Sik Kwak, Gil-Cho Ahn
A 12-bit 200-kS/s SAR ADC with hybrid RC DAC. APCCAS (2014)
Tai-Ji An, Jun-Sang Park, Yongmin Kim, Suk-Hee Cho, Gil-Cho Ahn, Seung-Hoon Lee
45nm CMOS ADC based on process-insensitive amplifiers. ISCAS (2013)
Yong-Sik Kwak, Kwang-Soo Kim, Gil-Cho Ahn
A 1.8 V 89.2 dB delta-sigma adc for sensor interface with on-chip reference. ISCAS (2012)
Jae-Hyeon Shin, Kang-Il Cho, Gil-Cho Ahn
A digitally enhanced low-distortion delta-sigma modulator for wideband application. ISOCC (2012)
Sang-Pil Nam, Yongmin Kim, Dong-Hyun Hwang, Hyo-Jin Kim, Tai-Ji An, Jun-Sang Park, Suk-Hee Cho, Gil-Cho Ahn, Seung-Hoon Lee
A 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC for analog TV applications. ISOCC (2012)
Young-min Park, Tae-In Kwon, Kang-Il Cho, Yong-Sik Kwak, Gil-Cho Ahn, Chang-Seob Shin, Myung-Jin Lee, Seung-Bin You, Ho-Jin Park
A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizer. ICECS (2012)
Chang-Seob Shin, Gil-Cho Ahn
A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique. IEEE Trans. Circuits Syst. II Express Briefs (5) (2011)
Jin-Seon Kim, Tae-In Kwon, Gil-Cho Ahn, Yi-Gyeong Kim, Jong-Kee Kwon
A ΔΣ ADC using 4-bit SAR type quantizer for audio applications. ISOCC (2011)
Byeong-Woo Koo, Seung-Jae Park, Gil-Cho Ahn, Seung-Hoon Lee
A Single Amplifier-Based 12-bit 100 MS/s 1 V 19 mW 0.13 µm CMOS ADC with Various Power and Area Minimized Circuit Techniques. IEICE Trans. Electron. (8) (2011)
Chang-Seob Shin, Min-Ho Yoon, Kang-Il Cho, Young-Ju Kim, Kwang-Soo Kim, Seung-Hoon Lee, Gil-Cho Ahn
A 6.25 MHz BW 8-OSR fifth-order single-stage sigma-delta ADC. ISCAS (2011)
Hee-Cheol Choi, Pil-Seon Yoo, Gil-Cho Ahn, Seung-Hoon Lee
0.13µm CMOS A/D converter for software-defined radio systems. Int. J. Circuit Theory Appl. 39 (2) (2011)
Xicheng Jiang, Jungwoo Song, Todd Brooks, Jianlong Chen, Vinay Chandrasekhar, Felix Cheung, Sherif Galal, Darwin Cheung, Gil-Cho Ahn, Madhulatha Bonu
A 10mW stereo audio CODEC in 0.13µm CMOS. ISSCC (2010)
Young-Ju Kim, Hee-Cheol Choi, Gil-Cho Ahn, Seung-Hoon Lee
A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp. IEEE J. Solid State Circuits 45 (3) (2010)
Seung-Hoon Lee, Young-Ju Kim, Hee-Cheol Choi, Gil-Cho Ahn
A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2009)
Young-Ju Kim, Hee-Cheol Choi, Kyung-Hoon Lee, Gil-Cho Ahn, Seung-Hoon Lee, Ju-Hwa Kim, Kyoung-Jun Moon, Michael Choi, Kyoung-Ho Moon, Ho-Jin Park, Byeong-Ha Park
A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers. CICC (2009)
Min-Gyu Kim, Gil-Cho Ahn, Pavan Kumar Hanumolu, Sanghyeon Lee, Sang-Ho Kim, Seung-Bin You, Jae-Whui Kim, Gabor C. Temes, Un-Ku Moon
A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC. IEEE J. Solid State Circuits 43 (5) (2008)
Gil-Cho Ahn, Min-Gyu Kim, Pavan Kumar Hanumolu, Un-Ku Moon
A 1V 10b 30MSPS Switched-RC Pipelined ADC. CICC (2007)
Jipeng Li, Gil-Cho Ahn, Dong-Young Chang, Un-Ku Moon
A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR. IEEE J. Solid State Circuits 40 (4) (2005)
Dong-Young Chang, Gil-Cho Ahn, Un-Ku Moon
Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2005)
Gil-Cho Ahn, Dong-Young Chang, Matthew E. Brown, Naoto Ozaki, Hiroshi Youra, Ken Yamamura, Koichi Hamashita, Kaoru Takasuka, Gábor C. Temes, Un-Ku Moon
A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators. IEEE J. Solid State Circuits 40 (12) (2005)
Min-Gyu Kim, Gil-Cho Ahn, Un-Ku Moon
An improved algorithmic ADC clocking scheme. ISCAS (1) (2004)
Gil-Cho Ahn, Hee-Cheol Choi, Shin-Il Lim, Seung-Hoon Lee, Chul-Dong Lee
A 12-b, 10-MHz, 250-mW CMOS A/D converter. IEEE J. Solid State Circuits 31 (12) (1996)