Daniel Eckerbert

Publication Activity (10 Years)

Years Active: 2000-2013
Publications (10 Years): 0

Top Topics

Aggregation Operators

Metal Oxide Semiconductor

Top Venues

IEEE J. Solid State Circuits

Publications

Lars Sundström, Staffan Ek, Jim Svensson, Martin Anderson, Roland Strandberg, Fenghao Mu, Imad ud Din, Thomas Olsson, Leif R. Wilhelmsson, Daniel Eckerbert
Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS. IEEE J. Solid State Circuits 48 (7) (2013)
Lars Sundström, Martin Anderson, Roland Strandberg, Staffan Ek, Jim Svensson, Fenghao Mu, Thomas Olsson, Imad ud Din, Leif R. Wilhelmsson, Daniel Eckerbert, Sven Mattisson
A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation. ISSCC (2013)
Martin Anderson, Roland Strandberg, Staffan Ek, Leif R. Wilhelmsson, Lars Sundström, Mattias Andersson, Imad ud Din, Jim Svensson, Thomas Olsson, Daniel Eckerbert
A 4.75-34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS. ESSCIRC (2012)
Lars Sundström, Staffan Ek, Jim Svensson, Martin Anderson, Roland Strandberg, Fenghao Mu, Imad ud Din, Thomas Olsson, Leif R. Wilhelmsson, Daniel Eckerbert
Complex IF harmonic rejection mixer for non-contiguous dual carrier reception in 65 nm CMOS. ESSCIRC (2012)
Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert
Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. IEEE Trans. Very Large Scale Integr. Syst. 14 (4) (2006)
Mindaugas Draidiiulis, Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson
A power cut-off technique for gate leakage suppression [CMOS logic circuits]. ESSCIRC (2004)
Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson
Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. ISVLSI (2003)
Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors
A Mixed-Mode Delay-Locked-Loop Architecture. ICCD (2003)
Daniel Eckerbert, Per Larsson-Edefors
A deep submicron power estimation methodology adaptable to variations between power characterization and estimation. ASP-DAC (2003)
Daniel Eckerbert, Per Larsson-Edefors
Interconnect-Driven Short-Circuit Power Modeling. DSD (2001)
Daniel Eckerbert, Per Larsson-Edefors
Cycle-true leakage current modeling for CMOS gates. ISCAS (5) (2001)
Daniel Eckerbert, Henrik Eriksson, Per Larsson-Edefors, Anders Edman
An interconnect-driven design of a DFT processor. ISCAS (2000)