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A power cut-off technique for gate leakage suppression [CMOS logic circuits].
Mindaugas Draidiiulis
Per Larsson-Edefors
Daniel Eckerbert
Henrik Eriksson
Published in:
ESSCIRC (2004)
Keyphrases
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logic circuits
low power
power consumption
power dissipation
cmos technology
nm technology
low voltage
functional decomposition
high speed
power management
low cost
leakage current
chip design
ultra low power
tunnel diode
gate array
digital signal processing
image sensor
logic synthesis
silicon on insulator