Chih-Chi Cheng

Publication Activity (10 Years)

Years Active: 2005-2016
Publications (10 Years): 1

Top Topics

Image Processing And Computer Vision

Curve Evolution

Top Venues

IEEE J. Solid State Circuits

Publications

Jason Clemons, Chih-Chi Cheng, Iuri Frosio, Daniel R. Johnson, Stephen W. Keckler
A patch memory system for image processing and computer vision. MICRO (2016)
Rahul Rithe, Chih-Chi Cheng, Anantha P. Chandrakasan
Quad Full-HD Transform Engine for Dual-Standard Low-Power Video Coding. IEEE J. Solid State Circuits 47 (11) (2012)
Rahul Rithe, Chih-Chi Cheng, Anantha P. Chandrakasan
Quad Full-HD transform engine for dual-standard low-power video coding. A-SSCC (2011)
Pei-Kuei Tsung, Pin-Chih Lin, Kuan-Yu Chen, Tzu-Der Chuang, Hsin-Jung Yang, Shao-Yi Chien, Li-Fu Ding, Wei-Yin Chen, Chih-Chi Cheng, Tung-Chien Chen, Liang-Gee Chen
A 216fps 4096×2160p 3DTV set-top box SoC for free-viewpoint 3DTV applications. ISSCC (2011)
Chih-Chi Cheng, Yi-Min Tsai, Liang-Gee Chen, Anantha P. Chandrakasan
A 0.077 to 0.168 nJ/bit/iteration scalable 3GPP LTE turbo decoder with an adaptive sub-block parallel scheme and an embedded DVFS engine. CICC (2010)
Chih-Chi Cheng, Po-Chih Tseng, Liang-Gee Chen
Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System. IEEE Trans. Circuits Syst. Video Technol. 19 (2) (2009)
Chih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Liang-Gee Chen
iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor. IEEE J. Solid State Circuits 44 (1) (2009)
Yi-Hau Chen, Chih-Chi Cheng, Tzu-Der Chuang, Ching-Yeh Chen, Shao-Yi Chien, Liang-Gee Chen
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine. IEEE Trans. Circuits Syst. Video Technol. 18 (1) (2008)
Chih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Samuel C. Chang, Liang-Gee Chen
iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor. DAC (2008)
Chih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Samuel C. Chang, Chia-Jung Hsu, Liang-Gee Chen
iVisual: An Intelligent Visual Sensor SoC with 2790fps CMOS Image Sensor and 205GOPS/W Vision Processor. ISSCC (2008)
Myong Hyon Cho, Chih-Chi Cheng, Michel A. Kinsy, G. Edward Suh, Srinivas Devadas
Diastolic arrays: throughput-driven reconfigurable computing. ICCAD (2008)
Yu-Wei Chang, Chih-Chi Cheng, Chun-Chia Chen, Hung-Chi Fang, Liang-Gee Chen
124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory. IEEE Trans. Circuits Syst. Video Technol. 17 (4) (2007)
Chih-Chi Cheng, Chao-Tsung Huang, Ching-Yeh Chen, Chung-Jr Lian, Liang-Gee Chen
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform. IEEE Trans. Circuits Syst. Video Technol. 17 (7) (2007)
Chia-Ping Lin, Po-Chih Tseng, Yao-Ting Chiu, Siou-Shen Lin, Chih-Chi Cheng, Hung-Chi Fang, Wei-Min Chao, Liang-Gee Chen
A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications. ISSCC (2006)
Yu-Wei Chang, Hung-Chi Fang, Chih-Chi Cheng, Chun-Chia Chen, Liang-Gee Chen
Precompression Quality-Control Algorithm for JPEG 2000. IEEE Trans. Image Process. 15 (11) (2006)
Hung-Chi Fang, Yu-Wei Chang, Chih-Chi Cheng, Liang-Gee Chen
Memory Efficient JPEG 2000 Architecture With Stripe Pipeline Scheduling. IEEE Trans. Signal Process. 54 (12) (2006)
Chih-Chi Cheng, Ching-Yeh Chen, Yi-Hau Chen, Liang-Gee Chen
Analysis and VLSI architecture of update step in motion-compensated temporal filtering. ISCAS (2006)
Yu-Wei Chang, Chih-Chi Cheng, Chun-Chia Chen, Hung-Chi Fang, Liang-Gee Chen
Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture. SiPS (2006)
Ching-Yeh Chen, Yi-Hau Chen, Chih-Chi Cheng, Liang-Gee Chen
Frame-level data reuse for motion-compensated temporal filtering. ISCAS (2006)
Yi-Hau Chen, Ching-Yeh Chen, Chih-Chi Cheng, Liang-Gee Chen
Scalable Rate-Distortion-Computation Hardware Accelerator for MCTF and ME. ICME (2006)
Chih-Chi Cheng, Chao-Tsung Huang, Jing-Ying Chang, Liang-Gee Chen
Line Buffer Wordlength Analysis for Line-Based 2-D DWT. ICASSP (3) (2006)
Yu-Wei Chang, Hung-Chi Fang, Chih-Chi Cheng, Chun-Chia Chen, Chung-Jr Lian, Shao-Yi Chien, Liang-Gee Chen
124Ms/s pixel-pipelined motion-JPEG 2000 codec without tile memory. ISSCC (2006)
Hung-Chi Fang, Yu-Wei Chang, Chih-Chi Cheng, Chun-Chia Chen, Liang-Gee Chen
Memory efficient JPEG2000 architecture with stripe pipeline scheme. ICASSP (5) (2005)
Chia-Ho Pan, I-Hsien Lee, Sheng-Chieh Huang, Chih-Chi Cheng, Chung-Jr Lian, Liang-Gee Chen
Application Layer Error Correction Scheme for Video Header Protection on Wireless Network. ISM (2005)
Chih-Chi Cheng, Chao-Tsung Huang, Po-Chih Tseng, Chia-Ho Pan, Liang-Gee Chen
Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT. ISCAS (5) (2005)