Po-Chih Tseng

Publication Activity (10 Years)

Years Active: 2001-2009
Publications (10 Years): 0

Publications

Chih-Chi Cheng, Po-Chih Tseng, Liang-Gee Chen
Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System. IEEE Trans. Circuits Syst. Video Technol. 19 (2) (2009)
Chung-Jr Lian, Po-Chih Tseng, Tung-Chien Chen, Yu-Wei Chang, Liang-Gee Chen
Reconfigurable architecture for video applications. SoCC (2007)
Chia-Ping Lin, Po-Chih Tseng, Yao-Ting Chiu, Siou-Shen Lin, Chih-Chi Cheng, Hung-Chi Fang, Wei-Min Chao, Liang-Gee Chen
A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications. ISSCC (2006)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform. IEEE Trans. Signal Process. 53 (4) (2005)
Chia-Ping Lin, Po-Chih Tseng, Liang-Gee Chen
Nearly Lossless Content-Dependent Low-Power DCT Design for Mobile Video Applications. ICME (2005)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters. J. VLSI Signal Process. 40 (2) (2005)
Po-Chih Tseng, Yung-Chi Chang, Yu-Wen Huang, Hung-Chi Fang, Chao-Tsung Huang, Liang-Gee Chen
Advances in Hardware Architectures for Image and Video Coding - A Survey. Proc. IEEE 93 (1) (2005)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method. IEEE Trans. Circuits Syst. Video Technol. 15 (7) (2005)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization. J. VLSI Signal Process. 40 (3) (2005)
Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems. J. VLSI Signal Process. 41 (1) (2005)
Chih-Chi Cheng, Chao-Tsung Huang, Po-Chih Tseng, Chia-Ho Pan, Liang-Gee Chen
Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT. ISCAS (5) (2005)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
Memory analysis and architecture for two-dimensional discrete wavelet transform. ICASSP (5) (2004)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
B-spline factorization-based architecture for inverse discrete wavelet transform. ISCAS (2) (2004)
Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
Reconfigurable discrete cosine transform processor for object-based video signal processing. ISCAS (2) (2004)
Siou-Shen Lin, Po-Chih Tseng, Liang-Gee Chen
Low-power parallel tree architecture for full search block-matching motion estimation. ISCAS (2) (2004)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform. IEEE Trans. Signal Process. 52 (4) (2004)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9, 7) filter bank. ICIP (2) (2003)
Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method. APCCAS (1) (2002)
Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
VLSI implementation of shape-adaptive discrete wavelet transform. VCIP (2002)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform. APCCAS (1) (2002)
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method. ISCAS (5) (2002)
Po-Chih Tseng, Chi-Kuang Chen, Liang-Gee Chen
CDSP: an application-specific digital signal processor for third generation wireless communications. IEEE Trans. Consumer Electron. 47 (3) (2001)