Low-power parallel tree architecture for full search block-matching motion estimation.
Siou-Shen LinPo-Chih TsengLiang-Gee ChenPublished in: ISCAS (2) (2004)
Keyphrases
- low power
- vlsi architecture
- power consumption
- high speed
- low cost
- cmos technology
- block matching motion estimation
- single chip
- nm technology
- mixed signal
- hardware architecture
- signal processor
- parallel processing
- low power consumption
- logic circuits
- real time
- computer vision
- efficient implementation
- low complexity
- data flow
- hardware implementation
- signal processing
- data management
- video sequences