Chia-Tung Ho

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 13

Top Topics

Sensitivity Analysis

Clustering Method

Design Automation

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Chia-Tung Ho, Haoxing Ren
Large Language Model (LLM) for Standard Cell Layout Design Optimization. CoRR (2024)
Chia-Tung Ho, Ajay Chandna, David Guan, Alvin Ho, Minsoo Kim, Yaguang Li, Haoxing Ren
Novel Transformer Model Based Clustering Method for Standard Cell Design Automation. ISPD (2024)
Chia-Tung Ho, Alvin Ho, Matthew Fojtik, Minsoo Kim, Shang Wei, Yaguang Li, Brucek Khailany, Haoxing Ren
NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model. ISPD (2023)
Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin
Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform. IEEE Access 10 (2022)
Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz
Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization. ASP-DAC (2022)
Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz
Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization. CoRR (2022)
Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Daeyeal Lee, Bill Lin
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis. IEEE Trans. Very Large Scale Integr. Syst. 30 (8) (2022)
Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin, Dongwon Park
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT. IEEE Trans. Very Large Scale Integr. Syst. 29 (6) (2021)
Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Bill Lin
Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning. SLIP (2021)
Daeyeal Lee, Dongwon Park, Chia-Tung Ho, Ilgweon Kang, Hayoung Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (10) (2021)
Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Dongwon Park
A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT. ICCAD (2020)
Chia-Tung Ho, Andrew B. Kahng
IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop. ICCAD (2019)
Yu-Min Lee, Chia-Tung Ho
InTraSim: Incremental Transient Simulation of Power Grids. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (12) (2017)
Chia-Tung Ho, Yu-Min Lee, Shu-Han Wei, Liang-Chia Cheng
Incremental transient simulation of power grid. ISPD (2014)
Shu-Han Wei, Yu-Min Lee, Chia-Tung Ho, Chih-Ting Sun, Liang-Chia Cheng
Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs. VLSI-DAT (2013)