Amitabha Sinha

Publication Activity (10 Years)

Years Active: 2009-2022
Publications (10 Years): 2

Top Topics

Linear Transformation

Fpga Implementation

Digital Signal Processors

Top Venues

SIGARCH Comput. Archit. News

Int. J. Softw. Innov.

Publications

Atri Sanyal, Amitabha Sinha
Trans_Proc: A Reconfigurable Processor to Implement The Linear Transformations. Int. J. Softw. Innov. 10 (1) (2022)
Atin Mukherjee, Amitabha Sinha, Debesh Choudhury
A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation. CoRR (2015)
Atin Mukherjee, Amitabha Sinha, Debesh Choudhury
A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation. SIGARCH Comput. Archit. News 42 (5) (2014)
Subhashis Maitra, Amitabha Sinha
Design and simulation of MAC unit using combinational circuit and adder. SIGARCH Comput. Archit. News 41 (5) (2013)
Amitabha Sinha, Mitrava Sarkar, Soumojit Acharyya, Suranjan Chakraborty
A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays. SIGARCH Comput. Archit. News 41 (2) (2013)
Subhashis Maitra, Amitabha Sinha
High efficiency MAC unit used in digital signal processing and elliptic curve cryptography. SIGARCH Comput. Archit. News 41 (4) (2013)
Amitabha Sinha, Soumojit Acharyya, Suranjan Chakraborty, Mitrava Sarkar
Field Programmable DSP Arrays - A CoRR (2013)
Santanu Pal, Amitabha Sinha, Pijush Biswas
FPGA implementation of a novel DCT architecture reducing constant cosine terms. SIGARCH Comput. Archit. News 41 (2) (2013)
Amrita Saha, Manideepa Mukherjee, Debanjana Datta, Sangita Saha, Amitabha Sinha
Performance analysis of a FPGA based novel binary and DBNS multiplier. SIGARCH Comput. Archit. News 41 (2) (2013)
Subhashis Maitra, Amitabha Sinha
High performance MAC unit for DSP and cryptographic applications. SIGARCH Comput. Archit. News 41 (2) (2013)
Amitabha Sinha, Mitrava Sarkar, Soumojit Acharyya, Suranjan Chakraborty
A Novel Reconfigurable Architecture of a DSP Processor for Efficient Mapping of DSP Functions using Field Programmable DSP Arrays. CoRR (2013)
Amrita Saha, Pijush Biswas, Amitabha Sinha
An integrated development platform of a reconfigurable radio processor for software defined radio. SIGARCH Comput. Archit. News 41 (2) (2013)
Aniruddha Ghosh, Satrughna Singha, Amitabha Sinha
A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system. SIGARCH Comput. Archit. News 40 (2) (2012)
Aniruddha Ghosh, Satrughna Singha, Amitabha Sinha
"Floating point RNS": a new concept for designing the MAC unit of digital signal processor. SIGARCH Comput. Archit. News 40 (2) (2012)
Chaitali Biswas Dutta, Partha Garai, Amitabha Sinha
A Scheme for Improving Bit Efficiency for Residue Number System. ACITY (3) (2012)
Chaitali Biswas Dutta, Partha Garai, Amitabha Sinha
Design Of A Reconfigurable DSP Processor With Bit Efficient Residue Number System CoRR (2012)
Subhashis Maitra, Amitabha Sinha
A new algorithm for computing triple-base number system. SIGARCH Comput. Archit. News 40 (4) (2012)
Nishant Kumar Giri, Amitabha Sinha
FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT. SIGARCH Comput. Archit. News 40 (2) (2012)
Satrughna Singha, Aniruddha Ghosh, Amitabha Sinha
A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique. SIGARCH Comput. Archit. News 39 (5) (2011)
Anindita Chakraborty, Amitabha Sinha
Conversion of binary to single-term triple base numbers for DSP applications. SIGARCH Comput. Archit. News 39 (5) (2011)
Malay Das, Amitabha Sinha, Nishant Kumar Giri
High speed residue number system (RNS) based FIR filter using distributed arithmetic (DA). SIGARCH Comput. Archit. News 39 (5) (2011)
Manideepa Mukherjee, Amitabha Sinha
A novel architecture for conversion of binary to single digit double base numbers. SIGARCH Comput. Archit. News 38 (5) (2010)
Sharbari Banerjee, Amitabha Sinha
A reconfigurable Digital Signal Processor using residue number system. ISSPA (2010)
Amrita Saha, Amitabha Sinha
An FPGA Based Architecture of a Novel Reconfigurable Radio Processor for Software Defined Radio. ICETC (2009)