A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays.
Amitabha SinhaMitrava SarkarSoumojit AcharyyaSuranjan ChakrabortyPublished in: SIGARCH Comput. Archit. News (2013)
Keyphrases
- systolic array
- reconfigurable architecture
- data flow
- digital signal processing
- signal processing
- digital signal processor
- parallel architecture
- high speed
- digital signal processors
- verilog hdl
- digital signal
- cost effective
- computer science
- parallel implementation
- single chip
- operating system
- pairwise
- pattern recognition
- database systems
- image processing
- neural network
- data sets