Design Of A Reconfigurable DSP Processor With Bit Efficient Residue Number System

Chaitali Biswas Dutta Partha Garai Amitabha Sinha

Published in: CoRR (2012)

Keyphrases

high speed
small number
low cost
case study
single chip
database systems
computational complexity
systolic array
image processing
data flow
design methodology
design considerations
digital signal processing
digital signal
reconfigurable architecture