Performance analysis of a FPGA based novel binary and DBNS multiplier.
Amrita SahaManideepa MukherjeeDebanjana DattaSangita SahaAmitabha SinhaPublished in: SIGARCH Comput. Archit. News (2013)
Keyphrases
- hardware implementation
- dynamic bayesian networks
- floating point
- belief nets
- non binary
- graphical models
- signal processing
- machine learning
- approximate inference
- graph cuts
- hardware architecture
- hardware design
- hamming distance
- particle filter
- distributed systems
- higher order
- multi class
- video sequences
- bayesian networks