Alpana Agarwal

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 19

Top Topics

Variable Resolution

Top Venues

J. Circuits Syst. Comput.

IET Circuits Devices Syst.

Circuits Syst. Signal Process.

Int. J. Circuit Theory Appl.

Publications

Abhishek Mishra, Anil Singh, Alpana Agarwal
Voltage Controlled Ring Oscillator with Phase Compensation Technique for Jitter Reduction in 180 nm CMOS Technology. J. Circuits Syst. Comput. 33 (8) (2024)
Naveen Kandpal, Anil Singh, Alpana Agarwal
An artificial intelligence-based 4-to-10-bit variable resolution Flash ADC with 3.6 to 1.04 GS/s sampling rate. Int. J. Circuit Theory Appl. 52 (8) (2024)
Ashima Gupta, Anil Singh, Alpana Agarwal
A Scalable Fully-Digital Differential Analog Voltage Comparator. J. Circuits Syst. Comput. 31 (4) (2022)
Naveen Kandpal, Anil Singh, Alpana Agarwal
A Machine Learning Driven PVT-Robust VCO with Enhanced Linearity Range. Circuits Syst. Signal Process. 41 (8) (2022)
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator. Int. J. Circuit Theory Appl. 50 (8) (2022)
Ashima Gupta, Anil Singh, Manu Bansal, Alpana Agarwal
Functional validation of highly synthesizable voltage comparator on FPGA. Integr. 84 (2022)
Amandeep Kaur, Sanjay Kumar, Ravinder Agarwal, Alpana Agarwal
Intra and inter-patient arrhythmia classification using feature fusion with novel feature set based on fractional-order and fibonacci series. Biomed. Signal Process. Control. 72 (Part) (2022)
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS. Circuits Syst. Signal Process. 41 (3) (2022)
Shivani Malhotra, Vinay Kumar, Alpana Agarwal
Bidirectional transfer learning model for sentiment analysis of natural language. J. Ambient Intell. Humaniz. Comput. 12 (11) (2021)
Shivani Malhotra, Vinay Kumar, Alpana Agarwal
Entropy optimized semi-supervised decomposed vector-quantized variational autoencoder model based on transfer learning for multiclass text classification and generation. CoRR (2021)
Amandeep Kaur, Sanjay Kumar, Alpana Agarwal, Ravinder Agarwal
An Efficient R-Peak Detection Using Riesz Fractional-Order Digital Differentiator. Circuits Syst. Signal Process. 39 (4) (2020)
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
A 2.3 mW Multi-Frequency Clock Generator with -137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology. J. Circuits Syst. Comput. 29 (8) (2020)
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology. J. Circuits Syst. Comput. 29 (9) (2020)
Ashima Gupta, Anil Singh, Alpana Agarwal
Implementation of Low Supply Rail-to-Rail Differential Voltage Comparator on Flexible Hardware for a Flash ADC. J. Circuits Syst. Comput. 29 (5) (2020)
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal
A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems. IntelliSys (1) (2019)
Ashima Gupta, Anil Singh, Alpana Agarwal
Highly-digital voltage scalable 4-bit flash ADC. IET Circuits Devices Syst. 13 (1) (2019)
Jupinder Kaur, Prince Prabhakar, Anil Singh, Alpana Agarwal
Fast digital foreground gain error calibration for pipelined ADC. IET Circuits Devices Syst. 13 (2) (2019)
Anil Singh, Ayushi Goel, Alpana Agarwal
A Digital-Based Low-Power Fully Differential Comparator. J. Circuits Syst. Comput. 26 (1) (2017)
Anil Singh, Veena Rawat, Alpana Agarwal
Low-power 10-bit 100 MS/s pipelined ADC in digital CMOS technology. IET Circuits Devices Syst. 11 (6) (2017)
Madhusoodan Agrawal, Alpana Agarwal
A Combined CMOS Reference Circuit with Supply and Temperature Compensation. VDAT (2013)
Alpana Agarwal, Chandra Shekhar
Synthesis of Analog IC Building Blocks. ISVLSI (2011)
Alpana Agarwal, Chandra Shekhar
Figure-of-Merit-Based Area-Constrained Design of Differential Amplifiers. VLSI Design 2008 (2008)
Varun Jindal, Alpana Agarwal
Carry Circuitry for LUT-Based FPGA. VLSI Design (2004)