A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS.
Jagdeep Kaur SahaniAnil SinghAlpana AgarwalPublished in: Circuits Syst. Signal Process. (2022)
Keyphrases
- user friendly
- cmos technology
- silicon on insulator
- camera calibration
- power consumption
- high resolution
- phase locked loop
- nm technology
- high speed
- low power
- low resolution
- image sequences
- analog vlsi
- foreground objects
- metal oxide semiconductor
- camera parameters
- calibration method
- focal length
- computer vision
- background subtraction
- foreground and background
- circuit design
- electron beam lithography
- concurrency control
- moving objects
- database systems