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Jagdeep Kaur Sahani
Publication Activity (10 Years)
Years Active: 2019-2022
Publications (10 Years): 5
Top Topics
High Resolution
Spl Times
Silicon On Insulator
Cmos Technology
Top Venues
J. Circuits Syst. Comput.
Int. J. Circuit Theory Appl.
Circuits Syst. Signal Process.
IntelliSys (1)
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Publications
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Jagdeep Kaur Sahani
,
Anil Singh
,
Alpana Agarwal
A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator.
Int. J. Circuit Theory Appl.
50 (8) (2022)
Jagdeep Kaur Sahani
,
Anil Singh
,
Alpana Agarwal
A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS.
Circuits Syst. Signal Process.
41 (3) (2022)
Jagdeep Kaur Sahani
,
Anil Singh
,
Alpana Agarwal
A 2.3 mW Multi-Frequency Clock Generator with -137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology.
J. Circuits Syst. Comput.
29 (8) (2020)
Jagdeep Kaur Sahani
,
Anil Singh
,
Alpana Agarwal
A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology.
J. Circuits Syst. Comput.
29 (9) (2020)
Jagdeep Kaur Sahani
,
Anil Singh
,
Alpana Agarwal
A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems.
IntelliSys (1)
(2019)