An efficient test-data compaction for low power VLSI testing.
Po-Han WuTsung-Tang ChenWei-Lin LiJiann-Chyi RauPublished in: EIT (2008)
Keyphrases
- test data
- low power
- high speed
- single chip
- vlsi circuits
- test cases
- power consumption
- gate array
- vlsi architecture
- low cost
- power dissipation
- test set
- search based testing
- training data
- logic circuits
- testing process
- high power
- mixed signal
- data sets
- training set
- wireless transmission
- low power consumption
- digital signal processing
- software testing
- training and test data
- signal processor
- image sensor
- data model
- nm technology
- training samples
- signal processing
- image processing
- test suite
- cmos technology
- computer vision
- real time