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Analyzing path delays for accelerated testing of logic chips.
Emily Ray
Barry P. Linder
Raphael Robertazzi
Kevin Stawiasz
Alan J. Weger
Emmanuel Yashchin
James H. Stathis
Peilin Song
Published in:
IRPS (2015)
Keyphrases
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chip design
shortest path
high speed
integrated circuit
test set
test cases
input output
endpoints
software testing
automated reasoning
defeasible logic
operating system
high density
probability theory
classical logic
predicate logic
multiple paths
artificial intelligence