A BIST Scheme for FPGA Interconnect Delay Faults.

Chun-Chieh Wang Jing-Jia Liou Yen-Lin Peng Chih-Tsun Huang Cheng-Wen Wu

Published in: VTS (2005)

Keyphrases

high speed
built in self test
test cases
fault diagnosis
low power
power dissipation
neural network
expert systems
wavelet transform
fault detection
hardware design
real time image processing