A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%.
Yuji YokoyamaNybutaka ItohMasap KatayamaKazumasa TakashimaHiroshi AkasakiMasayuki KanedaToshitsugu UedaYousuke TanakaEiji YamasakiMasaya TodokoroKeinosuke ToriyamaHiroshi MikiMasayoshi YagyuTom KobayashiSyuichi MiyaokaNobuo TambaPublished in: CICC (2000)
Keyphrases
- dynamic random access memory
- main memory
- hard disk
- memory usage
- secondary storage
- random access
- memory subsystem
- access control
- computational complexity
- high density
- data structure
- embedded systems
- storage devices
- building blocks
- database management systems
- low power
- memory requirements
- times faster
- flash memory
- routing protocol