Clear: c̲ross-l̲ayer e̲xploration for a̲rchitecting r̲esilience combining hardware and software techniques to tolerate soft errors in processor cores.
Eric ChengShahrzad MirkhaniLukasz G. SzafarynChen-Yong CherHyungmin ChoKevin SkadronMircea R. StanKlas LiljaJacob A. AbrahamPradip BoseSubhasish MitraPublished in: DAC (2016)
Keyphrases
- hardware and software
- low cost
- computer systems
- multi core processors
- error detection
- hardware software
- ibm zenterprise
- processor core
- level parallelism
- embedded processors
- parallel processing
- image processing
- software and hardware implementations
- parallel architectures
- multicore processors
- computing systems
- single chip
- hardware software co design
- programmable logic controller