Effects of MSHR and Prefetch Mechanisms on an On-Chip Cache of the Vector Architecture.
Akihiro MusaYoshiei SatoTakashi SogaRyusuke EgawaHiroyuki TakizawaKoki OkabeHiroaki KobayashiPublished in: ISPA (2008)
Keyphrases
- prefetching
- multithreading
- memory access
- memory subsystem
- mechanisms underlying
- vlsi implementation
- analog vlsi
- hit rate
- high speed
- host computer
- management system
- real time
- access patterns
- caching scheme
- low cost
- response time
- dynamic random access memory
- ibm zenterprise
- memory hierarchy
- design considerations
- data access
- feature vectors
- cmos technology
- level parallelism
- parallel computing
- high density
- processor core
- database management systems
- disk array