Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs.
Zoran JaksicRamon CanalPublished in: ICCD (2012)
Keyphrases
- leakage current
- cmos technology
- silicon on insulator
- low power
- low voltage
- power consumption
- dynamic random access memory
- electrical properties
- silicon dioxide
- parallel processing
- nm technology
- high speed
- low cost
- power line
- embedded dram
- power dissipation
- random access memory
- replacement policy
- power management
- data structure
- learning algorithm