A Fully Pipelined FPGA Architecture for Multiscale BRISK Descriptors With a Novel Hardware-Aware Sampling Pattern.
Sina GhaffariDavid W. CapsonKin Fun LiPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2022)
Keyphrases
- hardware architecture
- parallel architecture
- multiscale
- hardware implementation
- software implementation
- hardware design
- dedicated hardware
- field programmable gate array
- hardware architectures
- fpga technology
- xilinx virtex
- fpga implementation
- reconfigurable hardware
- real time
- associative memory
- fpga device
- low cost
- systolic array
- keypoints
- hardware software
- pattern matching
- signal processing
- data flow
- edge detection
- processing elements
- pipelined architecture
- general purpose processors
- parallel hardware
- scale space
- shared memory
- digital signal processing
- wavelet transform
- feature descriptors
- programmable logic
- digital signal processors
- vlsi implementation
- memory management
- high speed
- image segmentation
- image processing
- single chip
- distributed memory
- massively parallel
- computational power
- local binary pattern
- dense sampling
- efficient implementation
- image representation