Investigation of degradation mechanisms in low-voltage p-channel power MOSFETs under High Temperature Gate Bias stress.
Paolo MagnoneGiacomo BarlettaA. MagrìPublished in: Microelectron. Reliab. (2018)
Keyphrases
- low voltage
- high temperature
- cmos technology
- power consumption
- power management
- leakage current
- low power
- power dissipation
- silicon dioxide
- power line
- design considerations
- energy efficiency
- reactive power
- multi channel
- multiple input
- diesel engine
- field effect transistors
- energy saving
- data center
- parallel processing
- energy consumption
- digital signal processing