Reconfigurable Parallel VLSI Co-Processor for Space Robot Using FPGA.
R. WeiM. H. JinJ. J. XiaZongwu XieHong LiuPublished in: ROBIO (2006)
Keyphrases
- systolic array
- single chip
- high speed
- digital signal
- parallel architecture
- gate array
- hardware implementation
- parallel processing
- low cost
- field programmable gate array
- signal processing
- low power
- mobile robot
- computer architecture
- parallel hardware
- single processor
- processing elements
- parallel architectures
- multi core processors
- level parallelism
- parallel computing
- general purpose
- data flow
- robot navigation
- processor array
- position and orientation
- distributed memory
- vision system
- real time
- multiprocessor systems
- shared memory
- path planning
- multi processor
- multi robot
- search space
- efficient implementation
- reconfigurable hardware
- robotic systems
- digital signal processing
- humanoid robot
- autonomous robots
- parallel implementation
- human robot interaction