Si-Based Dual-Gate Field-Effect Transistor Array for Low-Power On-Chip Trainable Hardware Neural Networks.
Kyu-Ho LeeDongseok KwonIn-Seok LeeJoon HwangJiseong ImJong-Ho BaeWoo Young ChoiSung Yun WooJong-Ho LeePublished in: Adv. Intell. Syst. (2024)
Keyphrases
- low power
- field effect transistors
- low cost
- image sensor
- single chip
- high density
- chip design
- cmos technology
- steady state
- high speed
- power consumption
- low power consumption
- mathematical analysis
- signal processor
- schottky barrier
- mixed signal
- nm technology
- programmable logic
- power dissipation
- vlsi architecture
- digital signal processing
- hardware and software
- gate dielectrics
- wide dynamic range
- logic circuits
- vlsi circuits
- real time
- gate array
- content addressable memory
- solid state
- power reduction
- vlsi implementation
- cost effective
- cmos image sensor
- focal plane
- digital camera
- markov chain
- massively parallel
- embedded systems
- digital circuits