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Understanding Yield Losses in Logic Circuits.

Davide AppelloAlessandra FudoliKatia GiardaVincenzo TancorreEmil GizdarskiBen Mathew
Published in: IEEE Des. Test Comput. (2004)
Keyphrases
  • logic circuits
  • low power
  • gate array
  • low cost
  • logic synthesis
  • tunnel diode
  • case study
  • image analysis
  • fuzzy sets
  • efficient implementation
  • functional decomposition