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Understanding Yield Losses in Logic Circuits.
Davide Appello
Alessandra Fudoli
Katia Giarda
Vincenzo Tancorre
Emil Gizdarski
Ben Mathew
Published in:
IEEE Des. Test Comput. (2004)
Keyphrases
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logic circuits
low power
gate array
low cost
logic synthesis
tunnel diode
case study
image analysis
fuzzy sets
efficient implementation
functional decomposition