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Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit.
Yinhe Han
Yu Hu
Xiaowei Li
Huawei Li
Anshuman Chandra
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2007)
Keyphrases
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high speed
test cases
dynamic random access memory
real world
memory usage
memory management
parallel processing
black box
multi channel
software testing
circuit design
testing process
compute intensive
main memory
communication channels
computer architecture
computer systems