Low-power frequency monitoring circuit for clock failure detection.
Rodrigo B. CapeleiroJosé M. LeitãoRicardo ChavesMarcelino B. SantosPublished in: DCIS (2018)
Keyphrases
- failure detection
- low power
- high speed
- power consumption
- logic circuits
- power reduction
- cmos technology
- power dissipation
- fault detection
- duty cycle
- vlsi circuits
- gate array
- single chip
- low cost
- clock frequency
- real time
- low power consumption
- high power
- digital signal processing
- image sensor
- fault diagnosis
- vlsi architecture
- mixed signal
- delay insensitive
- ultra low power
- nm technology
- wireless transmission
- power saving
- fuzzy logic
- control system
- image processing