The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs.
Ming-Dou KerKun-Hsien LinPublished in: IEEE J. Solid State Circuits (2005)
Keyphrases
- cmos technology
- high voltage
- power dissipation
- low voltage
- power consumption
- low power
- high speed
- power reduction
- phase locked loop
- spl times
- circuit design
- operating conditions
- parallel processing
- mixed signal
- partial discharge
- normal operation
- duty cycle
- digital signal processing
- power management
- expert systems
- digital circuits
- design considerations
- steady state
- computer systems
- multi view
- moving objects