A CAD approach for on-chip PDN with power and supply noise reduction for multi-voltage SOCS in pre-layout stage.
Moumita ChakrabortyDebasri SahaAmlan ChakrabartiPublished in: ISED (2017)
Keyphrases
- noise reduction
- edge preserving
- signal to noise ratio
- solid models
- power losses
- noise level
- noisy environments
- median filter
- high speed
- ibm power processor
- edge detection
- edge enhancement
- chip design
- noise cancellation
- computer aided
- duty cycle
- power system
- power consumption
- electricity markets
- electrical power
- noise removal
- reactive power
- noise detection
- noise free
- hearing aids
- wiener filter
- power dissipation
- noise filtering
- speech enhancement
- edge preservation
- single phase
- high density
- input output
- multithreading
- bilateral filter
- median filtering