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CMOS Characterization and Compact Modelling for Circuit Reliability Simulation.
Javier Diaz-Fortuny
Javier Martín-Martínez
Rosana Rodríguez
Montserrat Nafría
Rafael Castro-López
Elisenda Roca
Francisco V. Fernández
Published in:
IOLTS (2018)
Keyphrases
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high speed
circuit design
analog vlsi
delay insensitive
reliability assessment
low voltage
cmos technology
chip design
vlsi circuits
simulation model
simulation environment
numerical simulations
low cost
neural network
analog circuits
frequency response
simulation study
power consumption
mathematical model
real time