HHC: Hierarchical hardware checkpointing to accelerate fault recovery for SRAM-based FPGAs.
Enshan YangKeheng HuangYu HuXiaowei LiJian GongHongjin LiuBo LiuPublished in: IOLTS (2013)
Keyphrases
- field programmable gate array
- failure recovery
- main memory databases
- hardware implementation
- error detection
- hardware software
- embedded systems
- distributed databases
- fault tolerance
- parallel architectures
- low cost
- real time
- hardware and software
- power consumption
- fault diagnosis
- reconfigurable hardware
- fault detection
- normal operation
- computing systems
- distributed database systems
- hardware architecture
- fpga implementation
- low power
- hardware design
- low overhead
- fpga technology
- main memory
- single link
- load balancing
- distributed systems
- log records
- error correction
- hierarchical clustering
- image processing