Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan Architecture.
Dong XiangDianwei HuQiang XuAlex OrailogluPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2009)
Keyphrases
- test data
- low power
- test cases
- power consumption
- low cost
- vlsi architecture
- test set
- high speed
- search based testing
- training data
- training set
- data sets
- cmos technology
- single chip
- testing process
- vlsi circuits
- mixed signal
- machine learning
- training and test data
- database
- logic circuits
- test data generation
- digital signal processing
- signal processor
- real time
- database systems
- nm technology
- gate array
- power reduction
- vlsi implementation
- power dissipation
- image sensor
- compression algorithm
- image compression
- data model