Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip.
Maurizio PalesiShashi KumarVincenzo CataniaPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2010)
Keyphrases
- high speed
- high bandwidth
- low cost
- missing links
- network structure
- high density
- heterogeneous networks
- heterogeneous information networks
- complex networks
- telecommunication networks
- link analysis
- programmable logic
- functional verification
- evolutionary algorithm
- chip design
- multiple faults
- terrorist networks
- vlsi implementation
- network topologies
- single chip
- circuit design
- network analysis