Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits.
Bipul C. PaulKaushik RoyPublished in: J. Electron. Test. (2006)
Keyphrases
- cmos technology
- power dissipation
- nm technology
- low power
- power consumption
- high speed
- analog vlsi
- delay insensitive
- circuit design
- vlsi circuits
- power reduction
- low voltage
- low cost
- chip design
- fault diagnosis
- fault model
- mixed signal
- logic circuits
- silicon on insulator
- digital signal processing
- image sensor
- design methodology
- human body
- neural network
- focal plane
- power management
- software testing
- fault models
- test cases
- variance reduction
- parallel processing
- video sequences