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A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories.
Hyungsu Sung
Keewon Cho
Kunsang Yoon
Sungho Kang
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2014)
Keyphrases
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real time
management system
associative memory
databases
content addressable
data flow
statistical tests
critical path
software architecture
hardware implementation
design considerations
defect classification