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A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits.
Abhishek Koneru
Sukeshwar Kannan
Krishnendu Chakrabarty
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2019)
Keyphrases
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integrated circuit
test data
website
multi objective
scheduling problem
test cases
scheduling algorithm
multi layer
statistical significance