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Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs.
Yu-Shih Su
Wing-Kai Hon
Cheng-Chih Yang
Shih-Chieh Chang
Yeong-Jar Chang
Published in:
ICCAD (2009)
Keyphrases
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duty cycle
high speed
power system
high voltage
objective function
sufficient conditions
steady state
power consumption
electric field
critical path
buffer size
electrical properties