Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs.
Daehyun KimSung Kyu LimPublished in: SLIP (2010)
Keyphrases
- prediction model
- power dissipation
- cmos technology
- power consumption
- low power
- regression model
- low cost
- high speed
- wavelet neural network
- neural network
- bp neural network
- predictive model
- response surface methodology
- bp network
- stepwise regression
- exponential smoothing
- digital signal processing
- input output
- power distribution
- silicon on insulator
- high density
- software reliability
- fiber optic
- customer churn
- silicon dioxide
- ls svm
- fuzzy neural network
- long term